Variable sized aperture window of an analog-to-digital converter

ABSTRACT

An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values. The digital output values could be the result of samplings all at the same frequency, or at different frequencies. Types of distributed sampling systems include a multitude of elongated trace patterns interconnected in series, a multitude of inverter pairs interconnected in series, a specific permittivity material device, and a sequencer or multiplier. A second enhanced sampling system includes a variable sized aperture window, wherein a width of a sample pulse is narrowed through a variable clock mechanism to produce a faster sampling rate. This variable sized aperture window system can be used by itself, or in combination with any of the presently described multiple ADC distributed sampling systems.

This application is a divisional of co-pending U.S. application Ser. No.11/800,708, filed May 7, 2007 by the same inventors (issued Aug. 11,2009 as U.S. Pat. No. 7,573,409), which claims priority to U.S.application Ser. No. 11/726,739, filed Mar. 22, 2007 by the sameinventors (issued May 5, 2009 as U.S. Pat. No. 7,528,756), both of whichare incorporated herein by reference in their entireties.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of computers and computerprocessors, and more particularly to analog-to-digital converters(ADCs).

2. Description of the Background Art

An analog-to-digital converter (ADC) is an electronic circuit thatconverts continuous signals to discrete digital numbers. Typically, anADC is an electronic device that converts an input analog voltage to adigital number.

The analog signal is continuous in time and it is necessary to convertthis to a flow of digital values. It is therefore required to define therate at which new digital values are sampled from the analog signal. Therate of new values is called the sampling rate or sampling frequency ofthe converter, and is typically reported as the number of samples persecond (sps).

A continuously varying bandlimited signal can be sampled at intervals oftime T, the sampling time, and measured and stored. The original signalcan then be exactly reproduced from the discrete-time values by aninterpolation formula. However, this reproduction is only possible ifthe sampling rate is higher than twice the highest frequency of thesignal. This is sometimes referred to as the Shannon-Nyquist samplingtheorem. Since a practical ADC cannot make an instantaneous conversion,the input value must necessarily be held constant during the time,called the conversion time, within which the converter performs aconversion.

It is often desirable to be able to sample analog signals in anintegrated circuit (IC) at very high frequencies, for example in therange of several gigahertz (GHz). However, certain types of ICs are madewith older semiconductor manufacturing and material technology that iscapable of sampling signals only at lower frequencies, for example inthe range of <1-2 GHz.

FIG. 1 is a diagrammatic representation of an example of ananalog-to-digital (A-to-D) sampling system 100 as is currently known inthe art. Embedded in chip 101 is the A-to-D block 102. A-to-D block 102has a data output 105, typically, but not necessarily a parallel bus,and a sampling frequency control 104, which is used to sample inputsignal 103. The highest frequency component of the input component is f,and the sampling frequency f_(s) must be at least twice the frequency off_(i), preferably 2.2 times the frequency of f_(i) for sampling thatsupports functions such as Fourier Transformations (FT) or Fast FourierTransformations (FFT), etc. Therefore, if the desired input frequencyf_(i) is in the 10 GHz range, the chip must be able to clock thesampling frequency f_(s) at approximately 20-22 GHz, based on theNyquist Frequency. Building a chip with such a high sampling frequencyis more costly, and the architecture of such chips does not permitembedding of large data functions such as CPUs, memory, etc. in such achip.

Several analog-to-digital conversion methods are known. FIG. 1A is aschematic representation of a sample and hold circuit diagram for anADC, which is also called a track and hold circuit. When the sample andhold switch 110 is open, the last instantaneous value of the inputvoltage is held on the sample and hold capacitor 111. When the sampleand hold switch 110 is closed, the circuit is in track mode. Buffers 112on the input and output isolate the sample and hold capacitor 111. Asample and hold ADC is simple and reliable, but is limited in itssampling frequency rate and it has a high error probability.

A second analog-to-digital conversion method is that which utilizes aphase detector ADC. A phase detector generates a voltage signal whichrepresents the difference in phase between two signal inputs. When thetwo compared signals are completely in phase, the two equal inputs to anXOR gate will output a constant level of zero. With a one degree phasedifference, the XOR gate will output a 1 for the duration of the signalsbeing different ( 1/360^(th) of the cycle). When the signals are 180degrees apart, the XOR gate puts out a steady 1 signal. Integration ofthe output signal results in an analog voltage proportional to the phasedifference. A phase detector contains a number of XOR gates thatsimultaneously measure a number of phase differences of the inputsignal. This has the advantage of being a fast acting device, but hasthe disadvantage of being a large power consumption device.

A third analog-to-digital conversion method is that which utilizes aflash ADC, which is also called a parallel ADC. FIG. 1B is a schematicrepresentation of a flash ADC circuit diagram. A flash ADC is formed ofa series of comparators 120, where each comparator 120 compares theinput signal to a unique reference voltage. The comparator 120 outputsconnect to the inputs of a priority encoder circuit 121, which thenproduces a binary output 122. As the analog input voltage exceeds thereference voltage at each comparator 120, the comparator 120 outputswill sequentially saturate to a high state. The priority encoder 121generates a binary number based on the highest order active input,ignoring all other active inputs. The flash ADC is efficient in terms ofspeed, but contains a large number of components. For example, athree-bit flash ADC requires eight comparators, a four-bit versionrequires 16 comparators, and an eight-bit version requires 256comparators.

A fourth analog-to-digital conversion method is a successiveapproximation ADC, schematically shown in FIG. 1C. The successiveapproximation ADC uses a successive approximation register (SAR) 130 asa sequence counter. This SAR 130 counts by trying all values of bitsstarting with the most significant bit (MSB) and finishing at the leastsignificant bit (LSB). Throughout the count process, the SAR 130monitors the comparator's output to see if the binary count is less thanor greater than the analog signal input, and then adjusts the bit valuesaccordingly. Different values of bits are tried from MSB to LSB to get abinary number that equals the original decimal number. Thedigital-to-analog converter (DAC) 131 output converges on the analogsignal input much faster than with a regular sequence counter. Thestoichastic renormalization group (SRG) 132 acts as a decimal to binaryconverter. The successive approximation ADC is a faster device, but hasthe disadvantages of high power consumption and a large number ofcomponents.

Various approaches have been taken to find an economical system that cansample high frequency input rates. In an article entitled, Design of aHigh-Performance Analog-to-Digital Converter, by Kevin Nary, publishedin CSD Magazine in October 1998, Nary discloses a folding andinterpolating 8-bit 2-Gsps ADC. The number of comparators required for a4-bit ADC is reduced from fifteen to six when switching from a flash toa folding architecture. This ADC increases the analog bandwidth and themaximum sample rate and consumes less power than a flash architectureADC. One method of achieving a folding function uses cross-coupled,differential amplifiers, where a single fold is achieved with twocross-coupled, differential amplifiers. By adding more resistors anddifferential pairs, the number of folds may be increased. Nary reportedresults of a 2 GHz sampling frequency with 98 MHz input frequency.

Another approach has been disclosed in an article entitled, CapturingData from Gigasample Analog-to-Digital Converters, by Ian King,published in I/O Magazine in January 2006, which discloses a method ofde-multiplexing the digital output. For a 1.5 GHz sample rate, theconversion data will be output synchronous to a 750 MHz clock, where thedata is presented to the outputs on both the rising and falling edges ofthe clock. Two latches are then used, wherein one latch is clocked onthe rising edge of the phase-locked data clock and a second latch isclocked using a signal that is 180 degrees out of phase. This reducesthe output to 375 MHz. After latching the incoming data, the clockdomain is shifted using an intermediate set of latches so that all ofthe data can be clocked into a memory array on the same clock edge,which de-multiplexes the data rate to 187.5 MHz. A single-channel devicecan be put into a dual-edge sampling mode to increase the sampling speedfrom 1.5 Gsps to 3.0 Gsps, which increases the number of output databits from 8 to 16. A system and method are clearly needed in which muchhigher sampling frequencies than 2-3 GHz can be converted.

SUMMARY OF THE INVENTION

It is an object of the present invention to adequately sample a veryhigh frequency input analog signal using circuitry which, otherwisemight not be able to sample at a sufficiently high rate.

An embodiment of the presently described invention includes a substratewith several ADCs and central processing units (CPUs), and a distributedsampling system. Each ADC works in conjunction with a designated CPU toform an ADC system. Each individual ADC system may contain conventionaldevices formed from 0.18 micron silicon, as an example. In this example,such individual systems are capable of sampling signals in the range of1-2 GHz or less.

The description of the present invention illustrates how multipleconventional devices can be used to adequately sample a very highfrequency input signal. A timing signal is passed through a distributedsampling system, also called a delay sampling system or a relay samplingsystem. When the timing signal reaches a first designated point alongthe distributed sampling system, a first ADC samples an input signal.When the timing signal reaches a second designated point along thedistributed sampling system, a second ADC samples the input signal. Thetiming signal continues through the distributed sampling system until anestablished number of samplings have been taken by the same establishednumber of ADC systems.

In the case when the devices are on a single chip, as in the presentexample, the timing signal is passed along the chip through thedistributed sampling system. The occurrence of each subsequent samplingoccurs at a clocked amount of time after the previous sampling. This isachieved by a plurality of sequential sampling prompts or tapsoriginating from the distributed sampling system as the timing signaltravels through the system. This results in cumulative samplings of thehigh frequency input signal by several ADCs, such that an adequatesampling necessary for optimum Nyquist-Shannon sampling is achieved. Forexample, if it is desired to adequately sample an input signal of 10 GHzusing conventional systems capable of only 1 GHz sampling, then 20 ADCsystems would be necessary in order to sequentially sample the inputanalog signal. In the present example, each ADC system obtains asampling at a clocked 50 psec interval after the previous sampling. Thesampling results of all 20 ADC systems are combined to obtain a resultthat produces essentially the same output as a single ADC system that iscapable of sampling at 20 GHz.

Several distributed sampling systems are described. One such distributedsampling system includes several elongated trace patterns or additionallengths of wire, which are electrically interconnected in series. Atiming signal travels through a first additional length of wire, afterwhich a timing signal tap or prompt causes a sampling of the inputsignal to be taken by a first ADC system; this occurs at a specifiedperiod of time, given by Δt. The timing signal continues through asecond additional length of wire, after which a timing signal tap orprompt causes a second sampling of the input signal to be taken by asecond ADC system; this occurs after a second period of time, Δt. Thetiming signal continues through an established number of lengths ofwire, which causes a cumulative sampling from the same establishednumber of ADC systems. The results of the sequential samplings are aseries of sequential digital output values from a plurality of ADCs. Thedigital output values could be the result of samplings all at the samefrequency, or at different frequencies.

Another example of a distributed sampling system includes a specifiedpermittivity material device, such as a SAW device. The material of thedevice determines the rate at which a timing signal travels through it.Samples of an input analog signal are taken by a plurality of ADCsystems when a timing signal reaches a plurality of equidistant pointsalong the device. The results of the sequential samplings are a seriesof sequential digital output values from a plurality of ADCs. Thedigital output values could be the result of samplings all at the samefrequency, or at different frequencies.

Still another example of a distributed sampling system uses a sequenceror multiplier, such that a timing signal is multiplied a set number oftimes in order to produce an incremental period of time, Δt for eachstage. The ADC systems sample an input analog signal after each periodof time, Δt. The input signal sampling results from the multipliersampling system are a series of sequential digital output values from aplurality of ADCs. The digital output values could be the result ofsamplings all at the same frequency, or at different frequencies.

An example of an ADC differential op amp circuit, which provides largecommon mode rejection is also described. By sampling the input signalout of phase, the input signal is completely differentiated and setapart from the background noise. This provides a cleaner signal, andtherefore more accurate sampling results.

Yet another example of an ADC circuit discloses an A-to-D cell, which isbased on a voltage controlled oscillator (VCO) circuit connected to aninput. The VCO output goes into a counter, where the output is thencompared to, or timed with a reference frequency through a gate, such asan XOR gate. The output then connects to a CPU, which also controlsresets of the counter.

An example of a variable sized aperture window sampling system is alsodescribed. This example is achieved through the utilization of avariable aperture clock, such as a resistor capacitor differentiatorcomprised of a voltage controlled resistor and a capacitor. Thisvariable aperture clock can modify the pulse width of a sample pulse toform a narrower pulse width, and therefore a faster sampling rate. Thisvariable sized aperture window sampling system can be used by itself forADC sampling, or it can be combined with any of the previously describedmultiple ADC distributed sampling systems.

These and other objects and advantages of the present invention willbecome clear to those skilled in the art in view of the description ofmodes of carrying out the invention, and the industrial applicabilitythereof, as described herein and as illustrated in the several figuresof the drawings. The objects and advantages listed are not an exhaustivelist of all possible advantages of the invention. Moreover, it will bepossible to practice the invention even where one or more of theintended objects and/or advantages might be absent or not required inthe application.

Furthermore, those skilled in the art will recognize that variousembodiments of the present invention may achieve one or more, but notnecessarily all, of the described objects and/or advantages.Accordingly, the objects and/or advantages described herein are notessential elements of the present invention, and should not be construedas limitations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagrammatic view of a conventional ADC system;

FIG. 1A is a circuit diagram of a sample and hold ADC;

FIG. 1B is a circuit diagram of a flash ADC;

FIG. 1C is a circuit diagram of a successive approximation ADC;

FIG. 2 is a block diagrammatic view of a general ADC system according tothe present invention;

FIGS. 3 a-3 b are representations of the timing relationship betweensamplings taken of an input analog signal and taps made in a timingsignal distributed line according to a first embodiment of the presentlydescribed invention;

FIG. 4 is a representation of the timing relationship between samplingstaken of an input analog signal and taps made in a timing signaldistributed line according to a second embodiment of the presentlydescribed invention;

FIGS. 5-6 are block diagrammatic views of a third embodiment of thepresently described invention;

FIGS. 7 a-7 b are circuit diagrams for an ADC that could be used withthe presently described invention;

FIG. 8 is a diagrammatic view of a computer array, according to thepresent invention;

FIG. 9 is a detailed diagram showing a subset of the computers of FIG. 8and a more detailed view of the interconnecting data buses of FIG. 8;

FIG. 10 is a block diagram depicting a general layout of a stackcomputer;

FIGS. 11 a-11 c are diagrammatic views of an ADC and computer systemarray according to the present invention;

FIG. 12 a is a circuit diagram of an ADC sampling system according tothe present invention;

FIG. 12 b shows input voltage vs. output frequency characteristics of aCMOS silicon process; and

FIG. 13 is a circuit diagram of an enhanced ADC sampling systemaccording to the present invention.

DETAILED DESCRIPTION

This invention is described with reference to the figures, in which likenumbers represent the same or similar elements. While this invention isdescribed in terms of modes for achieving this invention's objectives,it will be appreciated by those skilled in the art that variations maybe accomplished in view of these teachings without deviating from thespirit or scope of the presently claimed invention.

The embodiments and variations of the invention described herein, and/orshown in the drawings, are presented by way of example only and are notlimiting as to the scope of the invention. Unless otherwise specificallystated, individual aspects and components of the invention may beomitted or modified for a variety of applications while remaining withinthe spirit and scope of the claimed invention, since it is intended thatthe present invention is adaptable to many variations.

FIG. 2 shows an example of an ADC system 200 according to the presentinvention. An input signal 204 is passed into a number ofanalog-to-digital converter cells 202 _(a) through 202 _(n) of a chip201. An external sampling clock 205 is shown in this example, but aninternal clock could have been utilized as well. The sampling clock 205is run at a substantially lower frequency, for example, 10 or 20 timeslower frequency, than the intended sampling rate. By providingsequential time periods from time distribution apparatus 206 _(a)through 206 _(n), it is possible to increase the net sampling rate by nnumber of times. In this example, the time periods are provided by anexternal source, although as discussed above, an internal timing sourcecould also be utilized. If the input signal 204 with a frequency up to10 GHz is to be accurately sampled, then a sampling clock 205 at 20 or22 GHz would be necessary for optimum Nyquist-Shannon sampling. However,in the present inventive system, the sampling clock 205 can run at, forexample, 1 GHz for n=20 or 22, respectively. The time periods, providedby the time distribution apparatus 206 _(a) through 206 _(n) would be inan increment of 1/20, 1/22, or similar increment of the samplingfrequency, so that each ADC 202 would sample the input signal 204 at aslightly delayed point, resulting in a sampling that would be equivalentto using a single ADC, sampling at a rate of 20 or 22 GHz. The timeperiods, provided by the time distribution apparatus 206 _(a) through206 _(n) occur as a result of tap line connections 207 _(a) through 207_(n) between an individual distribution station (such as 206 _(a)) and acorresponding individual ADC (such as A/D 202 _(a)). When a timingsignal (produced by sampling clock 205) travels through a plurality ofserially connected distribution stations or distribution apparatus 206_(a) through 206 _(n) a series of taps or sampling prompts are sentthrough tap line connections 207 _(a) through 207 _(n) to correspondingADCs 202 _(a) through 202 _(n), respectively.

Such an approach would require a multitude of ADCs or A-to-D channels202, for example, in this case at least 20 or 22, but it would allow useof an older technology chip 201, for example 0.18 micron silicon, and itwould permit sampling of signals running in the 10 GHz range orthereabouts. By increasing the number of A-to-D channels 202 even more,the sampled signal frequency (or its highest Fourier Transformcomponent) could be even further increased.

Names of items 202 _(a) through 202 _(n) as ADCs, converter cells, orchannels have been used in this example interchangeably. Typically, tobe able to process the amount of data without losing sample data duringprocessing, each A-to-D channel 202 must have sufficient data transfercapabilities, for example its own CPU 203 _(a) through 203 _(n)corresponding to A-to-D channels 202 _(a) through 202 _(n).

The time period between each ADC sampling of the input signal could beachieved in various ways, as exemplified by the following embodiments.FIG. 3 a discloses a time relationship between samplings taken of aninput signal 301 and taps in a trace pattern 303 of a time distributedsampling system in a first embodiment of the invention. The tracepattern 303 contains a plurality of elongated wires connected in series.This time distributed sampling system has a plurality of ADC systems,wherein each ADC system comprises an ADC 202 and an associated centralprocessing unit (CPU) 203, as discussed previously in relation to FIG.2. When a timing signal 306 travels through a first length of wire 303 ato a tap point of W₁, a prompt to sample the input signal 301 after ameasurable amount of time, given by Δt 304 is made. This timing isrepresented as ADC sampling point C₁. As the timing signal 306 continuesthrough a second length of wire 303 b to a second tap point of W₂, aprompt to sample the input signal 301 after a second period of time, Δtis made. This timing is represented by ADC sampling point C₂. A separateADC system samples the input signal 301 after the timing signal 306reaches each trace pattern 303 at tap points, W₁ through W_(n) for eachtap in the distribution line. The results of the sequential samplingsare a series of sequential digital output values from a plurality ofADCs. The digital output values could be the result of samplings all atthe same frequency, or at different frequencies.

A more detailed explanation follows with reference to FIG. 3 a. A timingsignal 306 passes through a first length of wire, 303 a to a tap point,W₁. At that point in time, an input signal 301 is sampled by a first ADCsystem, represented in time by the ADC sampling point, C₁. When thetiming signal 306 travels through a second length of wire, 303 b to atap point represented by W₂, the input signal 301 is sampled by a secondADC system, at the ADC sampling point, C₂. The above describeddistributed sampling system continues to sample the input signal 301 atADC sampling points 302, designated in time by C₁, C₂, etc. The inputsignal 301 is sampled after each sequential time period, Δt 304 as thetiming signal 306 travels through the plurality of lengths of wire 303.A number of ADC systems are established on a chip in order to adequatelysample an input signal 301 in order to meet the Nyquist-Shannonrequirement.

Consider the following example, which is given to further clarify thepresent invention, wherein the given example is not to be construed as alimiting feature. If, for example, an input signal 301 of 10 GHzfrequency was to be sampled, then the time difference 304 between ADCsampling points 302 would need to be at least 50 psec to meet theNyquist-Shannon requirement for an adequate sampling rate of a 10 GHzinput signal. Each successive ADC system would sample the input signal301 at the sampling points C₁, C₂, etc., wherein each sampling wouldoccur at 50 psec after the previous ADC sampling. The ADC samplingpoints 302 correspond in time to successive tap points of W₁, W₂, etc.along the trace pattern 303. If each ADC system was capable of capturingor taking a sample every 1 nsec, then a total of 20 ADC systems would benecessary to adequately sample an incoming 10 GHz signal. In thisexample, the distributed sampling system using multiple lengths ofinterconnected wires of the presently described invention is equivalentto using a single ADC, which is capable of sampling an input signal of10 GHz at a sampling rate of 20 gsps.

FIG. 3 b discloses a time relationship between samplings taken of aninput signal 301 and taps made in a connected series of inverter pairs305 of a time distributed sampling system in a second embodiment of theinvention. Each clocked trace pattern 303 of FIG. 3 a is replaced with apair of inverters 305 in FIG. 3 b. A timing signal 306 travels through aseries of connected inverter pairs 305. When the timing signal 306travels through a first inverter pair 305 a, a prompt to sample theinput signal 301 after a first time period, Δt 304 is made, whichcoincides with the ADC sampling point C₁. As the timing signal 306continues through a second inverter pair 305 b, a prompt to sample theinput signal 301 after a second time period, Δt 304 is made, whichcoincides with the ADC sampling point, C₂. A separate ADC system samplesthe input signal 301 at each of the ADC sampling points, C₁ throughC_(n), which occurs when the timing signal 306 travels through eachinverter pair at points designated by W₁ through W_(n), respectively.The results of the sequential samplings are a series of sequentialdigital output values from a plurality of ADCs. The digital outputvalues could be the result of samplings all at the same frequency, or atdifferent frequencies.

A more detailed explanation follows with reference to FIG. 3 b. When atiming signal 306 travels through a first inverter pair, 305 a to a tappoint represented by W₁, an input signal 301 is sampled by a first ADCsystem at a first ADC sampling point, designated in time by C₁. When thetiming signal 306 travels through a second inverter pair, 305 b to a tappoint represented by W₂, the input signal 301 is sampled by a second ADCsystem at a second ADC sampling point, C₂. The above given distributedsampling system continues to sample the input signal 301 as the timingsignal 306 travels through the plurality of inverter pairs 305. As thetiming signal 306 travels through each of the inverter pairs 305, theinput signal 301 is sampled after each sequential time period, Δt 304 ateach ADC sampling point 302. A number of ADC systems are established ona chip in order to adequately sample an input signal 301 in order tomeet the Nyquist-Shannon requirement.

FIG. 4 discloses a time relationship between samplings taken of an inputanalog signal 405 and line taps made in a specific permittivity materialdevice 401 in a third embodiment of the invention. The time distributionsampling is achieved through the use of a specific permittivity materialdevice 401, such as a surface acoustic wave (SAW) device. An inputsignal 405 is sampled after each measurable time period, Δt 403 as atiming signal 406 travels past each equi-distant point, given by S₁through S_(n) along the device 401.

The specific permittivity material device distributed sampling systemrepresented by FIG. 4 works similar to the trace distributed samplingsystem of FIG. 3 a. A separate ADC system contains an ADC and acorresponding CPU, as previously described with reference to FIG. 2.Each sequential ADC system samples the input signal 405, represented byADC sampling points 402 when a timing signal 406 reaches each sequentialequi-distant point along the device 401, corresponding to points S₁through S_(n). As the timing signal 406 travels through the device 401,a prompt to sample the input signal 405 after each incremental timeperiod, Δt 403 is made, wherein the value of Δt 403 is determined by thespecific material of the device 401. When the timing signal 406 reachesa first sampling point 402 given by S₁, a prompt to sample the inputsignal 405 by a first ADC system at a first ADC sampling point, C₁ ismade. When the timing signal 406 reaches a second sampling point, S₂within the device 401 after a second time period, Δt 403 a second ADCsystem is prompted to sample the input signal 405 at the correspondingsecond ADC sampling point, C₂. The above described distributed samplingsystem continues to sample the input signal 405 at ADC sampling points402, which correspond in time to points, S₁ through S_(n) of the device401. The results of the sequential samplings are a series of sequentialdigital output values from a plurality of ADCs. The digital outputvalues could be the result of samplings all at the same frequency, or atdifferent frequencies.

In an example of using an input signal 405 of 10 GHz, a timing signal406 travels to a first point, given by S₁ within the device 401. At thispoint, a first ADC system is prompted to sample the input signal 405 atthe first ADC sampling point C₁ after a first time period 403 of 50psec. When the timing signal 406 travels to a second point S₂ within thedevice 401, a second ADC system is prompted to sample the input signal405 at a second sampling point, C₂ which will occur after a second timeperiod 403 of 50 psec. If each ADC system sampled the input signal 405at a rate of 1 nsec, then 20 ADC systems would be required to adequatelysample an input signal 405 of 10 GHz. In this example, the distributedsampling system using a specific permittivity material device of thepresently described invention is equivalent to using a single ADC, whichis capable of sampling an input signal of 10 GHz at a sampling rate of20 gsps.

A fourth embodiment discloses a sequencer or multiplier distributedsampling system 601, and is described with reference to FIG. 5. Anexample of a sequencer distribution sampling system 601 could use anemitter coupled logic (ECL) as a sequencer 501. The sequencer 501comprises a group of triggers 508 which are represented by w₁ throughw_(n). Each trigger 508 is connected to an ADC 502, each of which isthen connected to an associated CPU 506. A timing signal 507 enters thesequencer 501, then each stage sequences or multiplies the timing signal507 by the same incremental amount, given by Δt 503. Therefore, as apulse 504 travels through a first ADC trigger, w₁ the input signal 505is sampled by ADC₁. After a second time period Δt 503, a pulse 504travels through a second ADC trigger, w₂ wherein the input signal 505 issampled by ADC₂. The above described distributed sampling systemcontinues to sample the input signal 505 by utilizing n number oftriggers, w₁ through w_(n) and using ADC₁ through ADC_(n) converters,respectively. The sampling results are processed by n number ofassociated CPUs 506. The results of the sequential samplings are aseries of sequential digital output values from a plurality of ADCs. Thedigital output values could be the result of samplings all at the samefrequency, or at different frequencies. An important feature of thesequencer 501 is that time between each trigger 508 can be varied.

In an example of a 10 GHz input signal 505, the sequencer 501 comprises20 triggers 508, as represented by w₁ through w₂₀. The input analogsignal 505 will be sequentially sampled at intervals of 50 psec timeperiods, Δt 503. For example, ADC, will sample the input analog signal505 when a pulse 504 travels through a first ADC trigger, w₁ after afirst time period, Δt 503 of 50 psec. Then ADC₂ will sample the inputanalog signal 505 when a pulse 504 travels through a second ADC trigger,w₂ after a second time period, Δt 503 of 50 psec. If each ADC 502 iscapable of sampling an input analog signal 505 at a rate of 1 nsec, then20 triggers 508 along with 20 associated ADCs 502 and 20 associated CPUs506 would be necessary to adequately sample a 10 GHz input signal 505 ata sampling rate of 20 gsps. In this example, the distributed samplingsystem using multiple ADCs with a sequencer or multiplier of thepresently described invention is equivalent to using a single ADC, whichis capable of sampling an input signal of 10 GHz at a sampling rate of20 gsps.

FIG. 6 is a block diagram of a sequencer or multiplier distributedsampling system 601 which was described with reference to FIG. 5, withthe addition of a clock generating block 602. The clock generating block602 could be internal or external, and could include, but is not limitedto a phase locked loop (PLL), a delay locked loop (DLL), a voltagecontrolled oscillator (VCO), a ring oscillator, a crystal oscillator, orother type of oscillator. FIG. 6 also shows a timing signal 603.

FIG. 7 a is a circuit diagram 707 of an ADC that could be used with thepreviously described inventions, which utilizes differential op amps.The differential op amp system that is shown in FIG. 7 a has two inputsources 701 which are utilized in conjunction with op amps 702 a and 702b, wherein the op amp 702 b is a voltage to current driver with aselectable gain multiplier. This configuration provides large commonmode rejection for a very accurate reproduction of the input signal. Thesystem of FIG. 7 a further shows a counter 704, a CPU 705, and a digitaloutput signal 706.

FIG. 7 b is a circuit diagram 707 of an ADC which comprises asingle-ended voltage controlled oscillator 703. The remaining elementsare the same as for FIG. 7 a. The inverter system of FIG. 7 a has theadvantage of separating out the desired input signal 701 to be sampledfrom the undesirable background noise; FIG. 7 b has no noise immunity.However, the inverter system of FIG. 7 b requires only one pinconnection, whereas the inverter system of FIG. 7 a requires two pinconnections.

The ADC circuit diagrams of FIGS. 7 a and 7 b could be used with any ofthe previously described ADC/CPU distributed sampling systems forsampling an input analog signal.

The above described ADC/CPU distributed sampling systems could also beintegrated with any of various architectures well known to the inventor.One mode for carrying out the invention is through utilizing an array ofindividual computers. An array is depicted in a diagrammatic view inFIG. 8 and is designated therein by the general reference character 10.The computer array 10 has a plurality (twenty four in the example shown)of computers 12 (sometimes also referred to as “cores” or “nodes” in theexample of an array). In the example shown, all of the computers 12 arelocated on a single die 14. According to the present invention, each ofthe computers 12 is a generally independently functioning computer, aswill be discussed in more detail hereinafter. The computers 12 areinterconnected by a plurality (the quantities of which will be discussedin more detail hereinafter) of interconnecting data buses 16. In thisexample, the data buses 16 are bidirectional asynchronous high speedparallel data buses, although it is within the scope of the inventionthat other interconnecting means might be employed for the purpose. Inthe present embodiment of the array 10, not only can data communicationbetween the computers 12 be asynchronous, but the individual computers12 can also operate in an internally asynchronous mode. The individualcomputers 12 operate asynchronously, which saves a great deal of powersince each computer 12 will use essentially no power when it is notexecuting instructions, and since there is no clock running therein.

One skilled in the art will recognize that there will be additionalcomponents on the die 14 that are omitted from the view of FIG. 8 forthe sake of clarity. Such additional components include power buses,external connection pads, and other such common aspects of amicroprocessor chip.

Computer 12 e is an example of one of the computers 12 that is not onthe periphery of the array 10. That is, computer 12 e has fourorthogonally adjacent computers 12 a, 12 b, 12 c and 12 d. This groupingof computers 12 a through 12 e will be used, by way of example,hereinafter in relation to a more detailed discussion of thecommunications between the computers 12 of the array 10. As can be seenin the view of FIG. 8, interior computers 12 such as computer 12 e willhave four other computers 12 with which they can directly communicatevia the buses 16. In the following discussion, the principles discussedwill apply to all of the computers 12, except that the computers 12 onthe edge of the array 10 will be in direct communication with only threeother computers 12, and the corner computers 12 will be in directcommunication with only two other computers 12.

FIG. 9 is a more detailed view of a portion of FIG. 8 showing only someof the computers 12 and, in particular, computers 12 a through 12 e,inclusive. The view of FIG. 9 also reveals that the data buses 16 eachhave a read line 18, a write line 20 and a plurality (eighteen, in thisexample) of data lines 22. The data lines 22 are capable of transferringall the bits of one eighteen-bit instruction word simultaneously inparallel.

According to the present inventive method, a computer 12, such as thecomputer 12 e can set high one, two, three or all four of its read lines18 such that it is prepared to receive data from the respective one,two, three or all four adjacent computers 12. Similarly, it is alsopossible for a computer 12 to set one, two, three or all four of itswrite lines 20 high.

When one of the adjacent computers 12 a, 12 b, 12 c or 12 d sets a writeline 20 between itself and the computer 12 e high, if the computer 12 ehas already set the corresponding read line 18 high, then a word istransferred from that computer 12 a, 12 b, 12 c or 12 d to the computer12 e on the associated data lines 22. Then, the sending computer 12 willrelease the write line 20 and the receiving computer (12 e in thisexample) pulls both the write line 20 and the read line 18 low. Thelatter action will acknowledge to the sending computer 12 that the datahas been received. Note that the above description is not intendednecessarily to denote the sequence of events in order. In actualpractice, the receiving computer may try to set the write line 20 lowslightly before the sending computer 12 releases (stops pulling high)its write line 20. In such an instance, as soon as the sending computer12 releases its write line 20, the write line 20 will be pulled low bythe receiving computer 12 e.

Whenever a computer 12 such as the computer 12 e has set one of itswrite lines 20 high in anticipation of writing it will simply wait,using essentially no power, until the data is “requested”, as describedabove, from the appropriate adjacent computer 12, unless the computer 12to which the data is to be sent has already set its read line 18 high,in which case the data is transmitted immediately. Similarly, whenever acomputer 12 has set one or more of its read lines 18 to high inanticipation of reading it will simply wait, using essentially no power,until the write line 20 connected to a selected computer 12 goes high totransfer an instruction word between the two computers 12.

As discussed above, there may be several potential means and/or methodsto cause the computers 12 to function as described. However, in thispresent example, the computers 12 so behave simply because they areoperating generally asynchronously internally (in addition totransferring data there-between in the asynchronous manner described).That is, instructions are generally completed sequentially. When eithera write or read instruction occurs, there can be no further action untilthat instruction is completed (or, perhaps alternatively, until it isaborted, as by a “reset” or the like). There is no regular clock pulse,in the prior art sense. Rather, a pulse is generated to accomplish anext instruction only when the instruction being executed either is nota read or write type instruction (given that a read or write typeinstruction would require completion, often by another entity) or elsewhen the read or write type operation is, in fact, completed.

FIG. 10 is a block diagram depicting the general layout of an example ofone of the computers 12 of FIGS. 8 and 9. As can be seen in the view ofFIG. 10, each of the computers 12 is a generally self contained computerhaving its own RAM 24 and ROM 26. As mentioned previously, the computers12 are also sometimes referred to as individual “nodes”, given that theyare, in the present example, combined on a single chip.

Other basic components of the computer 12 are a return stack 28including an R register 29, an instruction area 30, an arithmetic logicunit (“ALU” or “processor”) 32, a data stack 34 and a decode logicsection 36 for decoding instructions. One skilled in the art will begenerally familiar with the operation of stack based computers such asthe computers 12 of this present example. The computers 12 are dualstack computers having the data stack 34 and the separate return stack28.

In this embodiment of the invention, the computer 12 has fourcommunication ports 38 for communicating with adjacent computers 12. Thecommunication ports 38 are further defined by the up port 38 a, theright port 38 b, the left port 38 c, and the down port 38 d. Thecommunication ports 38 are tri-state drivers, having an off status, areceive status (for driving signals into the computer 12) and a sendstatus (for driving signals out of the computer 12). If the particularcomputer 12 is not on the interior of the array (FIG. 8) such as theexample of computer 12 e, then one or more of the communication ports 38will not be used in that particular computer, at least for the purposesdescribed above. However, those communication ports 38 that do abut theedge of the die 14 can have additional circuitry, either designed intosuch computer 12 or else external to the computer 12 but associatedtherewith, to cause such communication port 38 to act as an external I/Oport 39 (FIG. 8). Examples of such external I/O ports 39 include, butare not limited to, USB (universal serial bus) ports, RS232 serial busports, parallel communications ports, analog to digital and/or digitalto analog conversion ports, and many other possible variations. Nomatter what type of additional or modified circuitry is employed forthis purpose, according to the presently described embodiment of theinvention, the method of operation of the “external” I/O ports 39regarding the handling of instructions and/or data received there fromwill be alike to that described, herein, in relation to the “internal”communication ports 38. In FIG. 8 an “edge” computer 12 f is depictedwith associated interface circuitry 80 (shown in block diagrammaticform) for communicating through an external I/O port 39 with an externaldevice 82.

In the presently described embodiment, the instruction area 30 includesa number of registers 40 including, in this example, an A register 40 a,a B register 40 b and a P register 40 c. In this example, the A register40 a is a full eighteen-bit register, while the B register 40 b and theP register 40 c are nine-bit registers. Also depicted in blockdiagrammatic form in the view of FIG. 10 is a slot sequencer 42.

The data stack 34 and the return stack 28 are not arrays in memoryaccessed by a stack pointer, as in many prior art computers. Rather, thestacks 34 and 28 are an array of registers. The top two registers in thedata stack 34 are a T register 44 and an S register 46. The remainder ofthe data stack 34 has a circular register array 34 a having eightadditional hardware registers therein numbered, in this example S₂through S₉. One of the eight registers in the circular register array 34a will be selected as the register below the S register 46 at any time.The value in the shift register that selects the stack register to bebelow S cannot be read or written by software. Similarly, the topposition in the return stack 28 is the dedicated R register 29, whilethe remainder of the return stack 28 has a circular register array 28 ahaving eight additional hardware registers therein (not specificallyshown in the drawing) that are numbered, in this example R₁ through R₈.

In addition to the registers previously discussed herein, theinstruction area 30 also has an 18 bit instruction register 30 a forstoring an instruction word that is presently being used, and anadditional 5 bit opcode register 30 b for the particular instructionword presently being executed.

The previously described ADC/CPU distributed sampling systems could beintegrated with the above described computer array, resulting innumerous system combinations of different type, size, and purpose. Inaddition, such systems could be processed as individual discretecomponents integrated together onto a substrate, or processed completelyon a single chip, or a combination of the two processes.

The following description will give two examples of different ADC arraypossibilities, which are given to further clarify the present inventionand are not to be construed as limiting features. FIG. 11 a shows a chipor die 14 with several computers or nodes 12. The interior computers 12are designated as general purpose computers (G) 94, which areinterconnected and therefore, can share resources there between aspreviously described. The periphery of the die 14 contains several ADCs(A) 95. Each ADC (A) 95 has a dedicated computer, referred to as an ADCcomputer (C) 96. Each ADC computer (C) 96 has access to any or all ofthe general purpose computers (G) 94. The connections between the ADCcomputers (C) 96 may or may not be utilized.

FIG. 11 b shows another embodiment of a die 14 with several computers12. ADCs (A) 95 are formed at the periphery of the die 14, but there areno dedicated ADC computers (C) 96 as in FIG. 11 a. Each ADC (A) 95 wouldhave direct access to any or all of the interconnected general purposecomputers (G) 94.

FIG. 11 c shows a die 14 with a total of forty computers 12, wherein 20computers 12 are ADCs (A) 95 and 20 computers 12 are general purposecomputers (G) 94. FIG. 11 c is an example of a die 14 which could beutilized in the previous examples of sampling a 10 GHz input analogsignal. Each individual ADC was capable of sampling at a rate of 1 gsps;therefore, 20 such ADCs (A) 95 and 20 associated general purposecomputers (G) 94 would be necessary to sample a 10 GHz input analogsignal.

FIG. 12 a is a circuit diagram of an ADC system 1200 according toanother embodiment of the current invention. A-to-D cell 202 is based ona voltage controlled oscillator (VCO) circuit using VCO 1201 connectedto input 204. The VCO output goes into a counter 1202, where the outputis then compared to, or timed with a reference frequency 1203 through agate, such as XOR gate 1204. The output then connects to a CPU 203,which also controls resets of the counter 1202 through line 1205.

The ADC circuit diagram of FIG. 12 a has combined the advantages of theprior art ADC conversion methods that were previously discussed above,and decreased or eliminated their disadvantages. The ADC circuit diagramof FIG. 12 a has the simplicity and reliability of the sample and holdcircuit of FIG. 1A, and the speed and accuracy of the phase detector,flash (FIG. 1B), and successive approximation (FIG. 1C) circuits. Thepresent inventive circuit of FIG. 12 a has a small number of components,and uses very little power compared to the fast circuits. The input 204of the present inventive ADC circuit is not limited to voltage sources,and it is not frequency dependent. There is no limitation on the rangeof the VCO 1201, and the counter 1202 is open to any speed or rate.

FIG. 12 b shows as diagram 1211 characteristics of a VCO 1201 in a CMOSsilicon process, such as 0.18 micron silicon. The input voltage range isfrom 0 to 1.8 volts, where the frequency moves from 1 GHz to 2 GHz.However, there is a narrow dynamic or useful range 1212 approximately 1or 1.2 volts wide. Transfer curve 1213 shows the input voltage on thex-axis and the output frequency in GHz on the y-axis.

FIG. 13 shows an enhanced sampling system 1300 according to anotherembodiment of the present invention. In A-to-D converter cell 202, theinput line 204 connects to an optional input buffer 1307. It thencontinues to an input sampling switch 1301, which connects tosample-and-hold capacitor 1302, whose voltage controls the VCO 1201.This approach allows the oscillator to run at a stable frequency betweensamplings. VCO 1201, in turn is connected to counter 1202, as describedabove which then has connections to CPU 203. CPU 203 also controls, inthis example a sample pulse, which it sends to buffer 1306. A variableaperture clock system, such as a resistor capacitor differentiator madeof a voltage-controlled resistor 1304 and a capacitor 1305 is utilized,where the resistor 1304 is voltage-adjustable. The CPU 203 causes adifferentiated, shorter pulse which is buffered in buffer 1303, and theCPU 203 also controls the input sampling switch 1301. By controlling theresistor voltage, the CPU 203 can modify the pulse width of the samplingperiod and create a smaller aperture window, and thereby increase thesampling rate.

The voltage controlled resistor 1304 and capacitor 1305 create aresistor capacitor differentiator, which determines the aperture windowsize or the variable rate for the input sampling switch 1301. The CPU203 modifies the pulse width of the sampling period by controlling theresistor 1304 voltage. The CPU 203 creates a differentiated, shorterpulse, and thereby controls the input sampling sample and hold switch1301. A shorter sample aperture window, which provides a shorter VCO1201 leads to the ability to sample higher frequency input signals. Avariable sample aperture window also resynchronizes the sampling phasesback together again, via a resynchronizing circuit.

Modifying the pulse width affects the settling time, etc. of thecapacitor, and thus affects the accuracy of the sampling. There is atrade-off between speed and accuracy, where a higher speed leads to aless accurate measurement. Therefore, resistor 1304 allows the system tohave a software control (not shown) for accuracy running as code in CPU203.

The presently described invention of a variable width aperture window,which provides a variable sampling rate, can be used by itself or incombination with any of the previously described time distributed ADCsampling systems. Therefore, each ADC of a multiple ADC distributedsampling system could also comprise a variable aperture clock, such as aresistor capacitor differentiator to provide a shorter pulse andtherefore, a shorter aperture window and a faster sampling rate.Likewise, the ADC variable rate aperture window sampling system could beused with any of the previously described multiple ADC distributedsampling system embodiments, including but not limited to the tracepattern embodiment described with reference to FIG. 3 a, the inverterpair embodiment described with reference to FIG. 3 b, the specificpermittivity material device embodiment described with reference to FIG.4, and the sequencer embodiment described with reference to FIGS. 5 and6.

All of the above examples are only some of the examples of availableembodiments of the present invention. Those skilled in the art willreadily observe that numerous other modifications and alterations may bemade without departing from the spirit and scope of the invention.Accordingly, the disclosure herein is not intended as limiting and theappended claims are to be interpreted as encompassing the entire scopeof the invention.

1. An analog-to-digital converter (ADC) circuit, comprising: a voltagecontrolled oscillator (VCO); a counter; a reference frequency source; aninput signal source; and a logic gate.
 2. The circuit of claim 1,further comprising a connection to a central processing unit (CPU). 3.The circuit of claim 2, wherein: an output of said VCO goes into saidcounter.
 4. The circuit of claim 3, wherein: said output is compared tosaid reference frequency through said gate.
 5. The circuit of claim 2,wherein: said CPU controls resets of said counter.
 6. The circuit ofclaim 1, wherein: said logic gate is an exclusive-OR (XOR) gate.
 7. Acomputer array, comprising: a substrate; an input signal source; a firstanalog-to-digital converter circuit integrated on said substrate andcoupled to said input signal source, said first analog-to-digitalconverter circuit including a VCO, a counter, a reference frequencysource; and a logic gate; a first computer integrated on said substrate,said first computer being coupled to said first analog-to-digitalconverter circuit; and a second computer integrated on said substrate.8. The computer array of claim 7, further comprising: a secondanalog-to-digital converter circuit integrated on said substrate andcoupled to said input signal source and to said second computer, saidsecond analog-to-digital converter circuit including a VCO, a counter, areference frequency source, a logic gate.
 9. The computer array of claim8, further comprising: a sampling clock signal source operative toprovide a clock signal; and a first time distribution apparatus coupledto said sampling clock signal source; and wherein said firstanalog-to-digital converter circuit is coupled to said first timedistribution apparatus.
 10. The computer array of claim 9, wherein saidsecond analog-to-digital converter circuit is coupled to said first timedistribution apparatus.
 11. The computer array of claim 9, wherein saidsecond analog-to-digital converter circuit is coupled to said timedistribution apparatus, said time distribution apparatus being operativeto increase the time it takes for said clock signal to reach said secondanalog-to-digital converter circuit with respect to the time it takesfor said clock signal to reach said first analog to digital converter.12. The computer array of claim 8, further comprising a data pathconnecting said first computer to said second computer.
 13. The computerarray of claim 8, further comprising: a third computer integrated onsaid circuit substrate; a fourth computer integrated on said circuitsubstrate; and a data path connection said third computer to said fourthcomputer.
 14. The computer array of claim 7, wherein said logic gate isan exclusive-OR (XOR) gate.
 15. The computer array of claim 7, whereinsaid VCO is operative to provide an output signal to said counter 16.The computer array of claim 15, wherein said logic gate is operative tocompare said output signal of said VCO with a reference frequencyprovided by said reference frequency source.
 17. The computer array ofclaim 7, wherein said first computer is operative to control saidcounter.
 18. The computer array of claim 7, wherein: said VCO includesan input and an output; said input of said VCO is coupled to said inputsignal source; and said output of said VCO is coupled to said counter.19. The computer array of claim 7, further comprising a secondanalog-to-digital converter circuit coupled to said input signal sourceand said second computer, said second analog-to-digital convertercircuit including: an input sampling switch; a sample and holdcapacitor; a variable aperture clock; a counter; and a VCO.